#hbUCPBackend

#define HB_UCP_CORE_ANY (0 << 0)
#define HB_UCP_BPU_CORE_0 (1ULL << 0)
#define HB_UCP_BPU_CORE_1 (1ULL << 1)
#define HB_UCP_BPU_CORE_2 (1ULL << 2)
#define HB_UCP_BPU_CORE_3 (1ULL << 3)
#define HB_UCP_BPU_CORE_ANY (1ULL << 7)
#define HB_UCP_DSP_CORE_0 (1ULL << 8)
#define HB_UCP_DSP_CORE_1 (1ULL << 9)
#define HB_UCP_DSP_CORE_ANY (1ULL << 15)
#define HB_UCP_GDC_CORE_0 (1ULL << 16)
#define HB_UCP_GDC_CORE_1 (1ULL << 17)
#define HB_UCP_GDC_CORE_ANY (1ULL << 19)
#define HB_UCP_STITCH_CORE_0 (1ULL << 20)
#define HB_UCP_LKOF_CORE_0 (1ULL << 24)
#define HB_UCP_JPU_CORE_0 (1ULL << 25)
#define HB_UCP_JPU_CORE_1 (1ULL << 26)
#define HB_UCP_JPU_CORE_2 (1ULL << 27)
#define HB_UCP_JPU_CORE_ANY (1ULL << 29)
#define HB_UCP_VPU_CORE_0 (1ULL << 30)
#define HB_UCP_VPU_CORE_1 (1ULL << 31)
#define HB_UCP_VPU_CORE_2 (1ULL << 32)
#define HB_UCP_VPU_CORE_ANY (1ULL << 33)
#define HB_UCP_PYRAMID_CORE_0 (1ULL << 35)
#define HB_UCP_PYRAMID_CORE_1 (1ULL << 36)
#define HB_UCP_PYRAMID_CORE_2 (1ULL << 37)
#define HB_UCP_PYRAMID_CORE_3 (1ULL << 38)
#define HB_UCP_PYRAMID_CORE_4 (1ULL << 39)
#define HB_UCP_PYRAMID_CORE_ANY (1ULL << 40)
#define HB_UCP_ISP_CORE_0 (1ULL << 42)
#define HB_UCP_ISP_CORE_1 (1ULL << 43)
#define HB_UCP_ISP_CORE_2 (1ULL << 44)
#define HB_UCP_ISP_CORE_3 (1ULL << 45)

Task execution hardware, can be used in combination, for example: HB_UCP_DSP_CORE_0 | HB_UCP_GDC_CORE_0 represents that the current task can use either the DSP 0 core or the GDC 0 core, the scheduling is leftto the UCP's own decision based on the load.

• Member

  Member Name	Description
  HB_UCP_CORE_ANY	Arbitrary executable hardware on Soc.
  HB_UCP_BPU_CORE_0	BPU core 0.
  HB_UCP_BPU_CORE_1	BPU core 1.
  HB_UCP_BPU_CORE_2	BPU core 2.
  HB_UCP_BPU_CORE_3	BPU core 3.
  HB_UCP_BPU_CORE_ANY	Arbitrary BPU core.
  HB_UCP_DSP_CORE_0	DSP core 0.
  HB_UCP_DSP_CORE_1	DSP core 1.
  HB_UCP_DSP_CORE_ANY	Arbitrary DSP core.
  HB_UCP_GDC_CORE_0	GDC core 0.
  HB_UCP_GDC_CORE_1	GDC core 1.
  HB_UCP_GDC_CORE_ANY	Arbitrary GDC core.
  HB_UCP_STITCH_CORE_0	STITCH core 0.
  HB_UCP_LKOF_CORE_0	LKOF core 0.
  HB_UCP_JPU_CORE_0	JPU core 0.
  HB_UCP_JPU_CORE_1	JPU core 1.
  HB_UCP_JPU_CORE_2	JPU core 2.
  HB_UCP_JPU_CORE_ANY	Arbitrary JPU core.
  HB_UCP_VPU_CORE_0	VPU core 0.
  HB_UCP_VPU_CORE_1	VPU core 1.
  HB_UCP_VPU_CORE_2	VPU core 2.
  HB_UCP_VPU_CORE_ANY	Arbitrary VPU core.
  HB_UCP_PYRAMID_CORE_0	PYRAMID core 0.
  HB_UCP_PYRAMID_CORE_1	PYRAMID core 1.
  HB_UCP_PYRAMID_CORE_2	PYRAMID core 2.
  HB_UCP_PYRAMID_CORE_3	PYRAMID core 3.
  HB_UCP_PYRAMID_CORE_4	PYRAMID core 4.
  HB_UCP_PYRAMID_CORE_ANY	Arbitrary PYRAMID core.
  HB_UCP_ISP_CORE_0	ISP core 0.
  HB_UCP_ISP_CORE_1	ISP core 1.
  HB_UCP_ISP_CORE_2	ISP core 2.
  HB_UCP_ISP_CORE_3	ISP core 3.