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  • 3.8.1

    • Environment Variable 

    // UCP
HB_UCP_LOG_LEVEL                       // Use hlog to set the ucp module log level, the value are 0, 1, 2, 3, 4, 5 and 6, corresponds respectively to trace, debug, info, warn, error, critical and never, default is warn
HB_UCP_LOG_PATH                        // Use hlog to set the log file path, support rolling and splitting feature, and can specify the size of a single file and the number of split files
HB_UCP_LOG_MAX_SIZE                    // Set the log file size when rolling and splitting, the unit is MB, and default is 1024
HB_UCP_LOG_ROTATE_NUM                  // Set the number of log files when rolling and splitting, and default is 16
HB_UCP_SCHEDULE_PRIORITY               // Set the priority of the ucp scheduler thread, the range of values is 0~99, default is 1. When the priority is set greater than 0, the thread scheduling method is SCHED_FIFO.
HB_UCP_CPU_PROCESS_THREAD_PRIORITY     // Set the CPU operator processing thread priority for ucp model inference. The value range is 0~99, and the default is 0. When the priority is set greater than 0, the thread scheduling mode is SCHED_RR
HB_UCP_ALL_BACKENDS_DEFAULT_DISABLE    // Disable all backends. If the value is not 0, it will be disabled, default is 0, which means it will not be disabled. This environment variable has a lower priority than all other environment variables HB_UCP_ENABLE_XXX_BACKEND_CORE_NUM that enable backends. The general usage is to disable all backends first, and then open the required backends individually
HB_UCP_ENABLE_GDC_BACKEND_CORE_NUM     // Set the number of cores that GDC can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off GDC which can reduce the occupation of thread resources
HB_UCP_ENABLE_STITCH_BACKEND_CORE_NUM  // Set the number of cores that STITCH can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off STITCH which can reduce the occupation of thread resources
HB_UCP_ENABLE_JPU_BACKEND_CORE_NUM     // Set the number of cores that JPEG Process Unit can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off JPU which can reduce the occupation of thread resources
HB_UCP_ENABLE_VPU_BACKEND_CORE_NUM     // Set the number of cores that Video Process Unit can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off Video Process Unit which can reduce the occupation of thread resources
HB_UCP_ENABLE_DSP_BACKEND_CORE_NUM     // Set the number of cores that DSP can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off DSP which can reduce the occupation of thread resources
HB_UCP_ENABLE_BPU_BACKEND_CORE_NUM     // Set the number of cores that BPU can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off BPU which can reduce the occupation of thread resources
HB_UCP_ENABLE_PYM_BACKEND_CORE_NUM     // Set the number of cores that PYM can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off PYM which can reduce the occupation of thread resources
HB_UCP_ENABLE_ISP_BACKEND_CORE_NUM     // Set the number of cores that ISP can support. The default is the maximum number of cores that the computing platform can support, Setting 0 will turn off ISP
HB_UCP_ENABLE_CPU_BACKEND_CORE_NUM     // Set the number of threads in the CPU operator thread pool for model inference, default is 6
HB_UCP_MAX_TASK_NUM                    // Set the maximum number of tasks that can exist simultaneously in each module of VP, HPL, and NN, default is 32
HB_UCP_SIM_PLATFORM_TYPE               // Set the computing platform type in the simulation environment. The values ​​are nash-e, nash-m, nash-p, nash-b, nash-b-plus, nash-b-lite and nash-h corresponding to different platform, default is nash-e
HB_UCP_ENABLE_LAZY_HLOG                // Controls the timing of hlog initialization. When set to 1, hlog won't initialize immediately after linking the libhbucp library (default value is 0). This setting applies to scenarios where only library linking is performed without interface invocation, avoiding memory overhead caused by hlog preallocation. Please note: when set to 1, hlog-related environment variables will not take effect, and subsequent ucp interface calls will only output error-level logs

// VP
HB_VP_LOG_LEVEL                        // Use hlog to set the vp module log level, the value are 0, 1, 2, 3, 4, 5 and 6, corresponds respectively to trace, debug, info, warn, error, critical and never, default is warn

// HPL
HB_HPL_LOG_LEVEL                       // Use hlog to set the hpl module log level, the value are 0, 1, 2, 3, 4, 5 and 6, corresponds respectively to trace, debug, info, warn, error, critical and never, default is warn

// DSP
HB_DSP_LOG_LEVEL                       // Set the DSP module ARM side log level, the value is 0, 1, 2, 3, 4, 5, 6, corresponding to Verbose, Debug, Info, Warning, Error, Critical, Never, the default is Warning
HB_DSP_VDSP_LOG_LEVEL                  // Set the DSP module DSP side log level, the value is 1, 2, 3, 4, 5, corresponding to Debug, Info, Warning, Error, Always, the default is Warning
HB_DSP_ENABLE_CONFIG_VDSP              // Set the ARM side configuration DSP side log level and log writing to ARM side display, the default is false
HB_DSP_WRITE_VDSP_LOG_TO_ARM           // Set the DSP side log ARM side display of the DSP end, the default is false

// NN
HB_NN_LOG_LEVEL                        // Use hlog to set the nn module log level, the value are 0, 1, 2, 3, 4, 5 and 6, corresponds respectively to trace, debug, info, warn, error, critical and never, default is warn
HB_NN_HBIR_GPU_ENABLE                  // Set whether to use GPU acceleration, `true` means use it.
HB_NN_ENABLE_MEM_LRU_CACHE             // Set whether the NN module uses memory LRU cache, `true` means it is used, and the default is not used.
HB_NN_MEM_LRU_CACHE_CLEAN_INTERVAL     // Set the time interval for the NN module to clean up the LRU cache in milliseconds. The default value is 1000ms.
HB_DNN_USER_DEFINED_L2M_SIZES          // Set the L2 Memory size allocated to each BPU core in the NN module. For example, in a 4-core BPU configuration: 6:6:6:6, which means 6MB is allocated to each core.

    Log Level Setting Instruction

    • Log level:

    The logs in UCP , VP , HPL and NN module are mainly divided into 7 levels:

    The log level can be set to 0, 1, 2, 3, 4, 5 and 6, corresponding to Verbose, Debug, Info, Warning, Error, Critical, and Never, with the default being Warning.

    The logs in DSP module ARM side are mainly divided into 7 levels:

    The log level can be set to 0, 1, 2, 3, 4, 5 and 6, corresponding to Verbose, Debug, Info, Warning, Error, Critical, and Never, with the default being Warning.

    The logs in DSP module DSP side are mainly divided into 5 levels:

    The log level can be set to 1, 2, 3, 4, 5, corresponding to Debug, Info, Warning, Error, Always, with the default being Warning.

    • Log level setting rules:

      • If the occurring log level is greater than or equal to the set level, then the log can be printed, otherwise, it will be shielded.
      • The smaller the set log level, the more information is printed. For example, if the log level is set to 3, which is the Warning level, then log at levels 3, 4, 5 can all be printed. The default log level of the VP module is Warning, i.e. the following log levels can be printed: Warning, Error, Critical.
    Note

    DSP side logs can be obtained by following the steps as belows:

    • Configure environment variables to enable DSP logging outputs.

      export HB_DSP_ENABLE_CONFIG_VDSP=true
export HB_DSP_WRITE_VDSP_LOG_TO_ARM=true

    • Start the log listening service.

      # VDSP0's logging service:
hrut_remoteproc_log -b /sys/class/remoteproc/remoteproc1/log

    HBIR Model Inference Instructions

    DNN supports inference of HBIR models in X86 environments. Since there may not be a GPU in your environment, GPU acceleration is not used by default.

    If there is a GPU on your machine, you can use GPU acceleration by setting the environment variable HB_NN_HBIR_GPU_ENABLE to true.

    Notes

    • When using GPU acceleration, make sure that the corresponding GPU driver and CUDA environment are installed on your machine. For environment requirements, please refer to Environment Deployment.

    • When using GPU acceleration, make sure libhbdnn.so is in the directory set by LD_LIBRARY_PATH.

    • When using GPU acceleration, you can set the deviceId in the control parameters to specify the GPU for calculation. Make sure the set value is in the range [0, gpu_dvice_count).

    Memory LRU Cache Description

    Before the BPU actually uses the BPU memory, the NN module needs to perform special processing on the memory before it can be used normally. Frequent processing of memory will increase the CPU load, which may cause performance problems.

    To solve this problem, the inference library provides a memory LRU cache function, which can be used by setting the environment variable HB_NN_ENABLE_MEM_LRU_CACHE to true. The setting method is as follows:

    export HB_NN_ENABLE_MEM_LRU_CACHE=true
    Note

    • The input and output memory are managed based on the LRU (least recently used principle) internally. Therefore, when using the cache function, the memory you applied for will not be released immediately after calling the release interface. The memory will not be actually released until the cache is cleaned. You can control the cache cleanup time interval by setting the HB_NN_MEM_LRU_CACHE_CLEAN_INTERVAL environment variable.

    • Scenario constraints: The memory you applied for will only be profitable when it is used repeatedly.

    • This cache feature is only available for NN modules.

    L2M Model Inference Support Guide

    The UCP-side L2 Cache uses a static mapping scheme. You need to configure the size of the L2 Cache allocated to each BPU core via the environment variable HB_DNN_USER_DEFINED_L2M_SIZES . Sizes for each core are separated by : and the unit is MB . The size values only support integers. During the inference preparation phase, UCP will allocate the L2 Cache for all cores according to your configuration. Below are several configuration examples and explanations:

    export HB_DNN_USER_DEFINED_L2M_SIZES=6:6:6:6    # Four cores, with 6MB allocated to each core
export HB_DNN_USER_DEFINED_L2M_SIZES=0:6:0:0    # Four cores, 6MB allocated to core 1, no allocation for the other cores
export HB_DNN_USER_DEFINED_L2M_SIZES=12:0:0:12  # Four cores, 12MB allocated to core 0, 12MB allocated to core 3, no allocation for the other cores
    Attention

    1. The inference of the L2M model is supported only on the J6P/H platform.

    2. When enabling L2 Cache optimization, inference priority cannot be set to preemptive priority.

    3. UCP supports L2 cache sharing between different processes. This feature depends on newer BSP versions; for specific version requirements, please consult the Horizon toolchain team. If you enable L2 cache sharing between processes, all processes must use the same allocation strategy, i.e., the values of the HB_DNN_USER_DEFINED_L2M_SIZES must be consistent across processes. If your BSP version does not support inter-process sharing, the sum of the L2 cache sizes configured for all processes must not exceed the maximum supported by the hardware.

    4. The maximum L2 cache size can be viewed using the command cat /sys/kernel/debug/ion/heaps/custom.